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Semiconductor
Semiconductor MSM518121A
131,072-Word 8-Bit Multiport DRAM
This version: Jan. 1998 MSM518121A Previous version: Dec. 1996
DESCRIPTION
The MSM518121A is an 1-Mbit CMOS multiport memory composed of a 131,072-words by 8-bit dynamic random access memory, RAM port, and a 256-word by 8-bit static serial access memory, SAM port. The RAM port and SAM port operate independently and asynchronously. The MSM518121A supports three types of operation: random access to and from the RAM port, high speed serial access to and from the SAM port and bidirectional transfer of data between any selected row in the RAM port and the SAM port. The RAM port and the SAM port can be accessed independently except when data is being transferred between them internally.
FEATURES
* Single power supply of 5 V 10% with a built-in VBB generator * All inputs and outputs :TTL compatible * Multiport organization RAM port : 128K word 8 bits SAM port : 256 word 8 bits * RAM port Fast page mode, Read modify write CAS before RAS refresh, Hidden refresh RAS only refresh, Standard write-per-bit * SAM port High speed serial Read / Write capabillity Fully static register 256 tap location * RAM-SAM bidirectional, Read / Write / Pseudo write, Real time read transfer * Package options: 40-pin 475 mil plastic ZIP (ZIP40-P-475-1.27) (Product : MSM518121A-xxZS) 40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM518121A-xxJS) xx indicates speed rank.
PRODUCT FAMILY
Family MSM518121A-70 MSM518121A-80 MSM518121A-10 Access Time RAM 70 ns 80 ns 100 ns SAM 25 ns 25 ns 25 ns Cycle Time RAM 140 ns 150 ns 180 ns SAM 30 ns 30 ns 30 ns Power Dissipation Operating 120 mA 110 mA 100 mA Standby 8 mA 8 mA 8 mA
1/33
Semiconductor
PIN CONFIGURATION (TOP VIEW)
W5/IO5 W7/IO7 SE SIO6 SIO8
1 3 5 7 9
2 4 6 8
W6/IO6 W8/IO8 SIO5 SIO7
SC 11 SIO2 13 SIO4 15 W1/IO1 17 W3/IO3 19 W4/IO4 21 WB/WE 23 A8 25 VSS2 27 A5 29 NC 31 A7 33 A2 35 A0 37 CAS 39
10 VSS1 12 SIO1 14 SIO3 16 DT/OE 18 W2/IO2 20 NC 22 VCC1 24 RAS 26 A6 28 NC 30 A4 32 VCC2 34 A3 36 A1 38 NC 40 NC

SC 1 SIO1 2 SIO2 3 SIO3 4 SIO4 5 DT/OE 6 W1/IO1 7 W2/IO2 8 W3/IO3 9 W4/IO4 10 VCC1 11 WB/WE 12 NC 13 RAS 14 NC 15 A8 16 A6 17 A5 18 A4 19 VCC2 20 40-Pin Plastic SOJ
MSM518121A
40 VSS1 39 SIO8 38 SIO7 37 SIO6 36 SIO5 35 SE 34 W8/IO8 33 W7/IO7 32 W6/IO6 31 W5/IO5 30 VSS2 29 NC 28 NC 27 CAS 26 NC 25 A0 24 A1 23 A2 22 A3 21 A7
40-Pin Plastic ZIP
Pin Name A0 - A8 RAS CAS DT / OE WB / WE W1/IO1 - W8/IO8 SC SE SIO1 - SIO8 VCC / VSS NC
Function Address Input Row Address Strobe Column Address Strobe Data Transfer / Output Enable Write per Bit / Write Enable Write Mask / Data IN, OUT Serial Clock Serial Enable Serial Input / Output Power Supply (5 V) / Ground (0 V) No Connection
Note:
The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/33
Semiconductor
MSM518121A
BLOCK DIAGRAM
W1/IO1 - W8/IO8 WB/WE
DT/OE
RAS
CAS
SC
SE
I/O Buffer (RAM)
Timing Generator
I/O Buffer (SAM)
Mask Register
Write/WPB Control
Column Decoder
Sense Amplifier
512 256 8 Cell Array
Column Address Buffer
Row Address Buffer
Refresh Counter
A0 - A8
Serial Address Counter VCC VSS
Row Decoder
Selector
SAM
SIO1 - SIO8
3/33
Semiconductor
MSM518121A
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Input Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT lOS PD Topr Tstg Condition Ta = 25C Ta = 25C Ta = 25C -- -- Rating -1.0 to 7.0 50 1 0 to 70 -55 to 150 (Note : 16) Unit V mA W C C
Recommended Operating Conditions
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min. 4.5 2.4 -1.0 Typ. 5.0 -- --
(Ta = 0C to 70C) (Note : 17) Max. 5.5 6.5 0.8 Unit V V V
Capacitance
Parameter Input Capacitance Input / Output Capacitance Symbol CI CI/O Min. -- --
(VCC = 5 V 10%, f = 1 MHz, Ta = 25C) Max. 7 9 Unit pF pF
Note :
This parameter is periodically sampled and is not 100% tested.
DC Characteristics 1
Parameter Output "H" Level Voltage Output "L" Level Voltage Input Leakage Current Symbol VOH VOL ILI Condition IOH = -2 mA IOL = 2 mA 0 VIN VCC All other pins not under test = 0 V 0 VOUT 5.5 V Output Disable Min. 2.4 -- -10 Max. -- 0.4 10 mA -10 10 Unit V
Output Leakage Current
ILO
4/33
Semiconductor DC Characteristics 2
Item (RAM) Operating Current (RAS, CAS Cycling, tRC = tRC min.) Standby Current (RAS, CAS = VIH) RAS Only Refresh Current (RAS Cycling, CAS = VIH, tRC = tRC min.) Page Mode Current (RAS = VIL, CAS Cycling, tPC = tPC min.) CAS before RAS Refresh Current (RAS Cycling, CAS before RAS, tRC = tRC min.) Data Transfer Current (RAS, CAS Cycling, tRC = tRC min.) SAM Standby Active Standby Active Standby Active Standby Active Standby Active Standby Active Symbol ICC1 ICC1A ICC2 ICC2A ICC3 ICC3A ICC4 ICC4A ICC5 ICC5A ICC6 ICC6A
MSM518121A
(VCC = 5 V 10%, Ta = 0C to 70C) -70 85 120 8 50 85 120 70 120 85 120 85 120 -80 75 110 8 45 75 110 65 110 75 110 75 110 -10 65 100 8 40 65 100 60 100 65 100 65 100 mA Max. Max. Max. Unit Note 1, 2 1, 2 3 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2
5/33
Semiconductor AC Characteristics (1/3)
Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from Column Address Access Time from CAS Access Time from CAS Precharge Output Buffer Turn-off Delay Transition Time (Rise and Fall) RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode Only) RAS Hold Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Time RAS to Column Address Delay Time Column Address to RAS Lead Time CAS to RAS Precharge Time CAS Precharge Time CAS Precharge Time (Fast Page Mode) Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time referenced to RAS Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Hold Time Write Command Hold Time referenced to RAS Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Symbol tRC tRWC tPC tPRWC tRAC tAA tCAC tCPA tOFF tT tRP tRAS tRASP tRSH tCSH tCAS tRCD tRAD tRAL tCRP tCPN tCP tASR tRAH tASC tCAH tAR tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL
MSM518121A
(VCC = 5 V 10%, Ta = 0C to 70C) Note 4, 5, 6 -70 140 195 45 90 -- -- -- -- 0 3 60 70 70 20 70 20 20 15 35 10 10 10 0 10 0 15 55 0 0 0 15 55 15 20 20 -- -- -- -- 70 35 20 40 20 35 -- 10k 100k -- -- 10k 50 35 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -80 150 195 50 90 -- -- -- -- 0 3 60 80 80 25 80 25 20 15 40 10 10 10 0 10 0 15 55 0 0 0 15 55 15 20 20 -- -- -- -- 80 40 25 45 20 35 -- 10k -- -- 10k 55 40 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -10 180 235 55 100 -- -- -- -- 0 3 70 100 25 100 25 20 20 55 10 10 10 0 10 0 15 70 0 0 0 15 70 15 25 25 -- -- -- -- 100 55 25 50 20 35 -- 10k -- -- 10k 75 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. Max. Min. Max. Min. Max. Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 13 13 7, 13 7, 13 7, 14 7, 14 9 6
100k 100 100k
6/33
Semiconductor AC Characteristics (2/3)
Parameter Data Set-up Time Data Hold Time Data Hold Time referenced to RAS Write Command Set-up Time RAS to WE Delay Time Column Address to WE Delay Time CAS to WE Delay Time Data to CAS Delay Time Data to OE Delay Time Access Time from OE Output Buffer Turn-off Delay from OE OE to Data Delay Time OE Command Hold Time RAS Hold Time referenced to OE CAS Set-up Time for CAS before RAS Cycle CAS Hold Time for CAS before RAS Cycle RAS Precharge to CAS Active Time Refresh Period WB Set-up Time WB Hold Time Write Per Bit Mask Data Set-up Time Write Per Bit Mask Data Hold Time DT High Set-up Time DT High Hold Time DT Low Set-up Time DT Low Hold Time DT Low Hold Time referenced to RAS (Real Time Read Transfer) DT Low Hold Time referenced to Column Address (Real Time Read Transfer) DT Low Hold Time referenced to CAS (Real Time Read Transfer) SE Set-up Time referenced to RAS SE Hold Time referenced to RAS DT to RAS Precharge Time DT Precharge Time RAS to First SC Delay Time (Read Transfer) Column Address to First SC Delay Time (Read Transfer) CAS to First SC Delay Time (Read Transfer) Last SC to DT Lead Time (Real Time Read Transfer) Symbol tDS tDH tDHR tWCS tRWD tAWD tCWD tDZC tDZO tOEA tOEZ tOED tOEH tROH tCSR tCHR tRPC tREF tWSR tRWH tMS tMH tTHS tTHH tTLS tTLH tRTH tATH tCTH tESR tREH tTRP tTP tRSD tASD tCSD tTSL
MSM518121A
(VCC = 5 V 10%, Ta = 0C to 70C) Note 4, 5, 6 -70 0 15 55 0 100 65 45 0 0 -- 0 10 10 15 10 10 0 -- 0 15 0 15 0 15 0 15 60 25 20 0 15 60 20 70 45 20 5 -- -- -- -- -- -- -- -- -- 20 10 -- -- -- -- -- -- 8 -- -- -- -- -- -- -- 10k 10k -- -- -- -- -- -- -- -- -- -- 0 15 55 0 100 65 45 0 0 -- 0 10 10 15 10 10 0 -- 0 15 0 15 0 15 0 15 65 30 25 0 15 60 20 80 45 25 5 -80 -- -- -- -- -- -- -- -- -- 20 10 -- -- -- -- -- -- 8 -- -- -- -- -- -- -- 10k 10k -- -- -- -- -- -- -- -- -- -- 0 15 70 0 130 80 55 0 0 -- 0 20 20 15 10 10 0 -- 0 15 0 15 0 15 0 15 80 30 25 0 15 70 30 100 50 25 5 -10 -- -- -- -- -- -- -- -- -- 25 20 -- -- -- -- -- -- 8 -- -- -- -- -- -- -- 10k 10k -- -- -- -- -- -- -- -- -- -- Min. Max. Min. Max. Min. Max. Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 9 12 12 12 12 11 11
7/33
Semiconductor AC Characteristics (3/3)
Parameter DT to First SC Delay Time (Read Transfer) Last SC to RAS Set-up Time (Serial Input) RAS to First SC Delay Time (Serial Input) RAS to Serial Input Delay Time Serial Output Buffer Turn-off Delay from RAS (Pseudo Write Transfer) SC Cycle Time SC Pulse Width (SC High Time) SC Precharge Time (SC Low Time) Access Time from SC Serial Output Hold Time from SC Serial Input Set-up Time Serial Input Hold Time Access Time from SE SE Pulse Width SE Precharge Time Serial Output Buffer Turn-off Delay from SE Serial Input to SE Delay Time Serial Input to First SC Delay Time Serial Write Enable Set-up Time Serial Write Enable Hold Time Serial Write Disable Set-up Time Serial Write Disable Hold Time Symbol tTSD tSRS tSRD tSDD tSDZ tSCC tSC tSCP tSCA tSOH tSDS tSDH tSEA tSE tSEP tSEZ tSZE tSZS tSWS tSWH tSWIS tSWIH
MSM518121A
(VCC = 5 V 10%, Ta = 0C to 70C) Note 4, 5, 6 -70 15 25 20 40 10 30 10 10 -- 5 0 15 -- 25 25 0 0 0 5 15 5 15 -- -- -- -- 40 -- -- -- 25 -- -- -- 25 -- -- 20 -- -- -- -- -- -- 15 25 20 40 10 30 10 10 -- 5 0 15 -- 25 25 0 0 0 5 15 5 15 -80 -- -- -- -- 40 -- -- -- 25 -- -- -- 25 -- -- 20 -- -- -- -- -- -- 15 30 25 50 10 30 10 10 -- 5 0 15 -- 25 25 0 0 0 5 15 5 15 -10 -- -- -- -- 50 -- -- -- 25 -- -- -- 25 -- -- 20 -- -- -- -- -- -- Min. Max. Min. Max. Min. Max. Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 8 8 9
8/33
Semiconductor Notes:
MSM518121A
1. These parameters depend on output loading. Specified values are obtained with the output open. 2. These parameters are masured at minimum cycle test. 3. ICC2 (Max.) are mesured under the condition of TTL input level. 4. VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 5. An initial pause of 200 ms is required after power-up followed by any 8 RAS cycles (DT/OE "high") and any 8 SC cycles before proper divice operation is achieved. In the case of using an internal refresh counter, a minimum of 8 CAS before RAS initialization cycles in stead of 8 RAS cycles are required. 6. AC measurements assume tT = 5 ns. 7. RAM port outputs are mesured with a load equivalent to 1 TTL load and 100 pF. Output reference levels are VOH/VOL = 2.4 V/0.8 V. 8. SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF. Output reference levels are VOH/VOL = 2.0 V/0.8 V. 9. tOFF (Max.), tOEZ (Max.), tSDZ (Max.) and tSEZ (Max.) difine the time at which the outputs achieve the open circuit condition and are not reference to output voltage levels. 10. Either tRCH or tRRH must be satisfied for a read cycle. 11. These parameters are referenced to CAS leading edge of early write cycles and to WB/WE leading edge in OE controlled write cycles and read modify write cycles. 12. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), the cycle is an early write cycle, and the data out pin will remain open circuit (high impedance) throughout the entire cycle : If tRWD tRWD (Min.), tCWD tCWD (Min.) and tAWD tAWD (Min.) the cycle is a read-write cycle and the data out will contain data read from the selected cell : If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indterminate. 13. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only : If tRCD is greater than the specified tRCD (Max.) limit, then access time is controlled by tCAC. 14. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only : If tRAD is greater than the specified tRAD (Max.) limit, then access time is controlled by tAA. 15. Input levels at the AC parameter measurement are 3.0 V/0 V. 16. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permenent damege to the device. 17. All voltages are referenced to VSS.
9/33
,,, ,
TIMING WAVEFORM
Read Cycle
tRC tRAS tRP RAS VIH - VIL - tAR tCSH tCRP tRCD tRSH tCPN CAS VIH - VIL - tCAS tASR tRAD tRAH tASC tRAL tCAH A0 - A8 VIH - VIL - Row Address Column Address tRCS tRCH tRRH WB/WE VIH - VIL - tTHS tTHH tROH VIH - DT/OE V IL - tDZO tOEA IN VIH - VIL - tCAC tOFF W1/IO1 W8/IO8 tAA tRAC tOEZ OUT VOH - VOL - Open Valid Data-out "H" or "L"
Semiconductor
MSM518121A
10/33
,,, , , ,
Semiconductor MSM518121A Write Cycle (Early Write)
tRC tRAS tRP RAS VIH - VIL - tAR tCSH tCRP tRCD tRSH tCPN VIH - CAS VIL - tCAS tRAD tRAL tASR tRAH tASC tCAH VIH - A0 - A8 VIL - Row Address tWSR Column Address tWCH tRWH tWCS WB/WE VIH - VIL - *1 tWP tWCR tTHS tTHH tCWL tRWL VIH - DT/OE V IL - tMS tMH tDS tDH IN VIH - VIL - WM1 Data Valid Data-in W1/IO1 W8/IO8 tDHR OUT VOH - VOL - Open "H" or "L"
*1 WB/WE 0 1
W1/IO1 - W8/IO8 WM1 data
Cycle
Write per Bit
Don't Care
Normal Write
WM1 data:
0: Write Disable 1: Write Enable
11/33
Semiconductor Write Cycle (OE Controlled Write)
MSM518121A
tRC tRAS RAS VIH - VIL - tCRP CAS VIH - VIL - tASR tRAD tRAH tASC tRCD tAR tCSH tRSH tCAS tRAL tCPN tRP
,, ,
tCAH VIH - A0 - A8 VIL - Row Address tWSR tRWH Column Address tCWL VIH - WB/WE VIL - *1 tRWL tWP tWCR tTHS tOEH VIH - DT/OE V IL - tMS tMH tDS tDH IN VIH - VIL - WM1 Data Valid Data-in W1/IO1 W8/IO8 tDHR OUT VOH- VOL - Open "H" or "L"
*1 WB/WE 0 1
W1/IO1 - W8/IO8 WM1 data
Cycle
Write per Bit
Don't Care
Normal Write
WM1 data:
0: Write Disable 1: Write Enable
12/33
Semiconductor Read Modify Write Cycle
MSM518121A
tRWC tRAS RAS VIH - VIL - tCRP VIH - CAS VIL - tRAD tASR tRAH tASC tCAH tRCD tAR tCSH tRSH tCAS tCPN tRP
, ,
VIH - A0 - A8 VIL - Row Address tWSR tRWH Column Address tCWL tWP tRCS tCWD tRWL VIH - WB/WE VIL - *1 tAWD tRWD tTHS tTHH tOEH VIH - DT/OE VIL - tMS tMH tDZC tDZO tDS tOED tDH IN VIH - VIL - WM1 Data tOEA Valid Data-in W1/IO1 W8/IO8 tRAC tAA tCAC tOEZ OUT VOH- VOL - Open Valid Data-out "H" or "L"
*1 WB/WE 0 1
W1/IO1 - W8/IO8 WM1 data
Cycle
Write per Bit
Don't Care
Normal Write
WM1 data:
0: Write Disable 1: Write Enable
13/33
Semiconductor Fast Page Mode Read Cycle
MSM518121A
tRASP RAS VIH - VIL - tCRP CAS VIH - VIL - tASR tAR tPC tRSH tRCD tRAD tCSH tRAH tASC tCAS tCP tCAS tASC tCAH tRAL tCP tCAS
tRP
tCPN
,, ,
tCAH tASC tCAH A0 - A8 VIH - VIL -
Row Address Column Address 1 Column Address 2 Column Address n
tRCH
tRCS
tRCH
tRCH
tRCS
tRCS
tRRH
VIH - WB/WE VIL -
tTHS
tTHH
VIH - DT/OE V IL -
tDZO
VIH - IN VIL -
tCPA
tCPA
tOEA
W1/IO1 W8/IO8
tCAC
tOFF
tOEA
tOFF
tOEA
OUT
VOH - VOL -
tRAC
tAA
tOEZ
tCAC
tAA
tOEZ
tCAC
tOFF
tAA
tOEZ
Open
Data-out 1
Data-out 2
Data-out n
"H" or "L"
14/33
Semiconductor Fast Page Mode Write Cycle (Early Write)
MSM518121A
tRASP RAS VIH - VIL - tCRP CAS VIH - VIL - tASR tRCD tRAD tCSH tRAH tASC tCAS tAR tPC tRSH tCP tCAS tCAH tRAL tCP tCAS
tRP
tCPN
, , , ,,,
tCAH tASC tASC tCAH A0 - A8 VIH - VIL -
Row Address Column Address 1 Column Address 2 Column Address n
tWCR
tWSR
tRWH
tWCH
tWCH
tWCS
tWCH
tWCS
tWCS
WB/WE
VIH - VIL -
tWP
tWP
tWP
tCWL
tCWL
tTHS
tTHH
tCWL tRWL
VIH - DT/OE V IL -
tMH
tMS
tDS
tDH
tDH
tDH
tDS
tDS
IN
VIH - VIL -
WM1 Data
Data-in 1
Data-in 2
Data-in n
W1/IO1 W8/IO8
tDHR
OUT
VOH - VOL -
Open
"H" or "L"
*1 WB/WE 0 1
W1/IO1 - W8/IO8 WM1 data
Cycle
Write per Bit
Don't Care
Normal Write
WM1 data:
0: Write Disable 1: Write Enable
15/33
Semiconductor Fast Page Mode Read Modify Write Cycle
MSM518121A
tRASP tAR RAS VIH - VIL - tRCD VIH - CAS VIL - tCAS tASC tASR tRAH
Row Address
tRP
tCSH tPRWC tCP tCAS tASC tASC tCP tCAS tCWL tRSH
, ,
tCAH tCWL tCAH tCWL tCAH tRWL A0 - A8 VIH - VIL -
Column Address 1 Column Address 2 Column Address n
WB/WE
tWSR VIH -
tRWH
tWP
tWP
tWP
VIL -
*1
tCWD tRWD
tCWD
tCWD
tTHS
tTHH
VIH - DT/OE V IL -
tRFH
tMH
tDZO
tDS
tDZO
tDS
tMS
tDZC
tOED
tDH
tDZC
tOED
tDZO
tDS
tDH
tDZC
tOED
tDH
IN
VIH - VIL -
WM1 Data
tOEA
Datain 1
tOEA
Datain 2
tOEA
Datain n
W1/IO1 W8/IO8
tCAC
tOEZ
tAA
tCAC tAA
tOEZ
tCAC tAA
tOEZ
VOH - OUT V OL -
tRAC
Dataout 1
Dataout 2
Dataout n
"H" or "L"
*1 WB/WE 0 1
W1/IO1 - W8/IO8 WM1 data
Cycle
Write per Bit
Don't Care
Normal Write
WM1 data:
0: Write Disable 1: Write Enable
16/33
Semiconductor RAS Only Refresh Cycle
MSM518121A
tRC tRAS RAS VIH - VIL - tCRP CAS VIH - VIL - tASR tRAH tRPC tCRP tRP
,,, ,
A0 - A8 VIH - VIL - Row Address WB/WE VIH - VIL - tTHS tTHH DT/OE VIH - VIL - W1/IO1 - VOH- W8/IO8 VOL - Open "H" or "L"
17/33
, ,
Semiconductor MSM518121A CAS before RAS Refresh Cycle
tRC tRP tRP VIH - RAS VIL - tRAS tRPC tCSR tCPN tCHR VIH - CAS VIL - WB/WE VIH - VIL - VIH - DT/OE V IL - tOFF W1/IO1 - VOH- W8/IO8 VOL - Open Note: A0 - A8 = Don't care ("H" or "L") "H" or "L"
18/33
Semiconductor Hidden Refresh Cycle
MSM518121A
tRC tRAS RAS VIH - VIL - tCRP VIH - CAS VIL - tAR tRP tRAS
tRC tRP
tRCD
tRSH
tCHR
tCPN
, ,
tRAD tASR tRAH tASC tRAL tCAH VIH - A0 - A8 VIL - Row Address Column Address tWSR tRCS tRRH tRWH WB/WE VIH - VIL - tTHS tTHH tROH DT/OE VIH - VIL - tOEZ tOFF tAA tOEA tCAC tOFF tOEZ W1/IO1 - VOH- W8/IO8 VOL - Valid Data-out "H" or "L"
19/33
Semiconductor Read Transfer Cycle (Previous Transfer is Write Transfer Cycle)
MSM518121A
,
tRC tRAS tRP RAS VIH - VIL - tAR tCSH tCRP tRCD tRSH tCPN VIH - CAS VIL - tCAS tRAD tRAL tASR tRAH tASC tCAH VIH - A0 - A8 VIL - Row Address SAM Start Address A0 - A7: TAP tWSR tRWH WB/WE VIH - VIL - tTRP tTLS tTLH tTP VIH - DT/OE V IL - tASD tOFF tCSD W1/IO1 - VOH - W8/IO8 VOL - tRSD tTSD tSCC tSRS tSCP tSC tSCP SC VIH - VIL - Inhibit Rising Transient tSC tSDS tSDH tSZS IN VIH - VIL - Valid Data-in SIO1 SIO8 tSCA tSOH OUT VOH - VOL - Valid Data-out Note: SE = VIL "H" or "L"
20/33
Semiconductor Real Time Read Transfer Cycle
MSM518121A
,,, ,
tRC tRAS tRP VIH - RAS VIL - tAR tCSH tCRP tRCD tRSH tCAS tCPN VIH - CAS VIL - tRAD tRAL tASR tRAH tASC tCAH VIH - A0 - A8 VIL - Row Address tRWH SAM Start Address A0 - A7: TAP tATH tWSR WB/WE VIH - VIL - tCTH tTRP tTLS tRTH tTP VIH - DT/OE V IL - tOFF W1/IO1 - VOH - W8/IO8 VOL - tSCC tSC tSCP tTSL tTSD SC VIH - VIL - IN VIH - VIL - Open SIO1 SIO8 tSCA tSCA tSOH tSOH OUT VOH - VOL - Valid Data-out Valid Data-out Valid Data-out Valid Data-out Valid Data-out Previous Row Data New Row Data Note: SE = VIL "H" or "L"
21/33
Semiconductor Pseudo Write Transfer Cycle
MSM518121A
, , ,
tRC tRAS tRP VIH - RAS VIL - tAR tCSH tCRP tRCD tRSH tCPN CAS VIH - VIL - tCAS tRAD tRAL tASR tRAH tASC tCAH VIH - A0 - A8 VIL - Row Address SAM Start Address A0 - A7: TAP tWSR tRWH WB/WE VIH - VIL - tTLS tTLH VIH - DT/OE V IL - tOFF W1/IO1 - VOH - W8/IO8 VOL - Open tSRD tSCC tSRS tSCP tSC tSCP SC VIH - VIL - Inhibit Rising Transient tSC tESR tREH tSWS VIH - SE VIL - tSDD tSDZ tSDS tSDH IN VIH - VIL - tSEZ SIO1 SIO8 tSCA Valid Data-in VOH - OUT V - OL Valid Data-out tSOH Valid Data-out Open Serial Output Data Serial Input Data "H" or "L"
22/33
Semiconductor Write Transfer Cycle
MSM518121A
, , ,
tRC
tRAS
tRP
RAS
VIH - VIL -
tAR
tCSH
tCRP
tRCD
CAS
VIH - VIL -
tRSH tCAS
tCPN
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH - A0 - A8 VIL -
Row Address
SAM Start Address A0 - A7: TAP
tWSR
tRWH
WB/WE
VIH - VIL -
tTLS
tTLH
VIH - DT/OE V IL -
tOFF
W1/IO1 - VOH - W8/IO8 VOL -
Open
tSRD
tSCC
tSRS
tSCP
tSC
tSCP
SC
VIH - VIL -
Inhibit Rising Transient
tSC
tESR
tREH
tSWS
SE
VIH - VIL -
tSDS
tSDH
tSDS
tSDH
IN
VIH - VIL -
Valid Data-in
Valid Data-in
Valid Data-in
SIO1 SIO8
VOH - OUT V - OL
Open
Previous Row Data
New Row Data
"H" or "L"
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, ,, , ,, ,
Semiconductor MSM518121A Serial Read Cycle (SE = VIL)
RAS VIH - VIL - tTHS tTHH VIH - DT/OE V IL - tSCC tSCC tSCC tSCC tSCC tSC tSC tSC tSC tSC SC VIH - VIL - tSCP tSCA tSCP tSCA tSCP tSCA tSCP tSCA tSCP tSCA tSCP tSOH tSOH tSOH tSOH tSOH SIO1 - VOH - SIO8 VOL - Valid Data-out Valid Data-out Valid Data-out Valid Data-out Valid Data-out Valid Data-out Note: SE = VIL "H" or "L"
Serial Read Cycle (SE Controlled Outputs)
VIH - VIL -
RAS
tTHS
tTHH
VIH - DT/OE V IL -
tSCC
tSCC
tSCC
tSCC
tSCC
tSC
tSC
tSC
tSC
tSC
VIH - SC VIL -
tSCP
tSCP
tSEP
tSCP
tSCP
tSCP
tSCP
SE
VIH - VIL -
tSZE
IN
VIH - VIL -
SIO1 SIO8
tSCA
tSEA
tSCA
tSCA
tSOH
tSEZ
tSCA
tSOH
tSOH
OUT
VOH - VOL -
Valid Data-out
Valid Data-out
Open
Valid Data-out
Valid Data-out
Valid Data-out
"H" or "L"
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, , , ,, ,
Semiconductor MSM518121A Serial Write Cycle (SE = VIL)
RAS VIH - VIL - tTHS tTHH VIH - DT/OE V IL - tSCC tSCC tSCC tSCC tSCC tSC tSC tSC tSC tSC VIH - SC VIL - tSDH tSDH tSDH tSDH tSDH tSCP tSCP tSCP tSCP tSCP tSCP tSDS tSDS tSDS tSDS tSDS SIO1 - VIH - SIO8 VIL - Valid Data-in Valid Data-in Valid Data-in Valid Data-in Valid Data-in Note: SE = VIL "H" or "L"
Serial Write Cycle (SE Controlled Inputs)
RAS VIH - VIL -
tTHS
tTHH
VIH - DT/OE VIL -
tSCC
tSCC
tSCC
tSCC
tSCC
tSC
tSC
tSC
tSC
tSC
VIH - SC VIL -
tSCP
tSCP
tSCP
tSCP
tSCP
tSCP
tSWS
tSWIH tSEP
SE
VIH - VIL -
tSWH
tSWS tSWH tSE tSDH
tSWIH tSEP
tSWS tSWH
tSDS
tSE tSDH
tSWIS
tSWIS
tSDS
tSDS
tSE tSDH
IN
VIH - VIL -
Valid Data-in
Valid Data-in
Valid Data-in
SIO1 SIO8
VOH - OUT V OL -
Open
"H" or "L"
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Semiconductor
MSM518121A
Address Input : A0 - A8 The 17 address bits decode an 8-bit location out of the 131,072 locations in the MSM518121A memory array. The address bits are multiplexed to 9 address input pins (A0 to A8) as standard DRAM. Nine row address bits are latched at the falling edge of RAS. The following eight column address bits are latched at the falling edge of CAS. Row Address Strobe : RAS RAS is a basic a RAM control input signal. The RAM port is in standby mode when the RAS level is "high". As the standard DRAM's RAS signal function, RAS is the control input that latches the row address bits are a random access cycle begins at the falling edge of RAS. In addition to the conventional RAM signal functions, the level of the input signals, CAS, DT/ OE, WB/WE, and SE, at the falling edge of RAS, determines the MSM518121A operation modes. Column Address Strobe : CAS As the standard DRAM's CAS signal function, CAS is the control input signal that latches the column address input and acts as an RAM port output enable signal. Data Transfer / Output Enable : DT / OE DT/OE is also a control input signal having multiple functions. As the standard DRAM's OE signal function, DT/OE is used as an output enable control when DT/OE is "high" at the falling edge of RAS. In addition to the conventional OE signal function, a data transfer operation is started between the RAM port and the SAM port when the DT/OE is "low" at the falling edge of RAS. Write-per-Bit / Write Enable : WB / WE WB/WE is a control input signal having multiple functions. As the standard DRAM's WE signal function, it is used to write data into the memory array on the RAM port when WB/WE is "high" at the falling edge of RAS. In addition to the conventional WE signal function, the WB/WE determines the write-per-bit function when WB /WE is "low" at the falling edge of RAS, during RAM port operations. The WB/WE also determines the direction of data transfer between the RAM and SAM. When WB/ WE is "high" at the falling edge of RAS, the data is transferred from RAM to SAM (Read transfer). When WB/WE is "low" at the falling edge of RAS, the data is transferred from SAM to RAM (Write transfer).
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Semiconductor Write Mask Data / Data Input and Mask Data : W1 / IO1 - W8 / IO8
MSM518121A
W1/ IO1 to W8 / IO8 have the functions of both Input/Output and a control input signal. As the standard DRAM's I/O pins, input data on the W1/IO1 to W8/IO8 are written into the RAM port during the write cycle. The input data is latched at the falling edge of either CAS or WB/WE, whichever occurs later. The RAM data out buffers, which will output read data from the W1/IO1 to W8 /IO8 pins, become low impedance state after the specified access times from RAS, CAS, DT / OE and column address are satisfied and the output data will remain vaild as long as CAS and DT/OE are kept "low". The outputs will return to the high-impedance state at the rising edge of either CAS or DT/OE, whichever occurs earlier. In addition to the conventional I/O functions, the W1/IO1 to W8/IO8 have the funnction to set the mask data, which select mask input pins out of eight input pins, W1/ IO1 to W8/IO8, at the falling edge of RAS. Data is written in to the DRAM on data lines where the write-mask data is a logic "1". Writing is inhibited on data lines where the write-mask data is a logic "0". The writemask data is valid for only one cycle. Serial Clock : SC SC is a main serial cycle contorol input signal. All operations of the SAM port are synchronized with the serial clock SC. Data is shifted in or out of the SAM registers at the rising edge of SC. In a serial read, the output data becomes valid on the SIO pins after the maximum specified serial access time tSCA from the rising edge of SC. The serial lock SC also increments the 8 bits serial pointer which is used to select the SAM address. The pointer address is incremented in a wrap-around mode to select sequential locations after the setting location which is determined by the column address in the read transfer cycle. When the pointer reaches the most significant address location (Decimal 255), the next SC clock will place it at the least significant address location (Decimal 0). The serial clock SC must be held data constant VIH or VIL level during read/pseudo write/write transfer operations and should not be clocked while the SAM port is in the standby mode to prevent the SAM pointer from being incremented. Serial Enable : SE The SE is a serial access enable control and serial read/write control input signal. In a serial read cycle, SE is used as an output control. In a serial write cycle, SE is used as a write enable control. When SE is "high", serial access is disable, however, the serial address pointer location is still incremented when SC is clocked even when SE is "high". Serial Input / Output : SIO1 - SIO8 Serial input/output mode is determined by the most recent read, write or pseudo write transfer cycle. When a read transfer cycle is performed, the SAM port is in the output mode. When a write or pseudo write transfer cycle is performed, the SAM port is switched from output mode to input mode.
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Semiconductor
MSM518121A
Fast Page Mode Cycle Fast page mode allows data to be transferred into or out multiple column locations of the same row by performing multiple CAS cycle during a single active RAS cycle. During a fast page cycle, the RAS signal may be maintained active for a period up to 100 seconds. For the initial fast page mode access, the output data is valid after the specified access times from RAS, CAS, column address and DT/OE. For all subsequent fast page mode read operations, the output data is valid after the specified access times from CAS, column address and DT/OE. When the write-per-bit function is enabled, the mask data latched at the falling edge of RAS is maintained throughout the fast page mode write or Read-Modify-Write cycle. RAS-Only Refresh The data is the DRAM requires periodic refreshing to prevent data loss. Refreshing is accomplished by performing a memory cycle at each of the 512 rows in the DRAM array within the specified 8 ms refresh period. Although any normal memory cycle will perform the refresh operation, this function is most easily accomplished with "RAS-Only" cycle. CAS before RAS Refresh The MSM518121A also offers an internal-refresh function. When CAS is held "low" for a specified period (tCSR) before RAS goes "low", an internal refresh address counter and on-chip refresh control clock generators are enabled and an internal refresh operation takes place. When the refresh operation is completed, the internal refresh address counter is automatically incremented in preparation for the next CAS-before-RAS cycle. For successive CAS-before-RAS refresh cycle, CAS can remain "low" while cycling RAS. Hidden Refresh A hidden refresh is a CAS-before-RAS refresh performed by holding CAS "low" from a previous read cycle. This allows for the output data from the previous memory cycle to remain valid while performing a refresh. The internal refresh address counter provides the address and the refresh is accomplished by cycling RAS after the specified RAS-precharge period. Write-per-Bit Function The Write-Per-Bit selectively controls the internal write-enable circuits of the RAM port. WritePer-Bit is enabled when WB/WE held "low" at the falling edge of RAS in a random write operation. Also, at the falling edge of RAS, the mask data on the Wi/IOi pins are latched into a write mask register. The write mask data must be presented at the Wi/IOi pins at every falling edge of RAS. A "0" on any of the Wi/IOi pins will disable the corresponding write circuits and new data will not be written into the RAM. A "1" on any of the Wi/IOi pins will enable the corresponding write circuits and new data will be written into the RAM.
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Semiconductor DATA TRANSFER OPERATION
MSM518121A
The MSM518121A features an internal data transfer capability between RAM and the SAM. During a transfer cycle, 256 words by 8 bits of data can be loaded from RAM to SAM (Read Transfer) or from SAM to RAM (Write Trasfer). The MSM518121A supports three types of transfer operations: Read transfer, Write Transfer and pseudo write transfer. Data transfer operations between RAM and SAM are invoked by holding the DT/OE signal "low" at the falling edge of RAS, the type of data transfer operation is determined by the state of CAS, WB/WE and SE latched at the falling edge of RAS. During data transfer operations, the SAM port is switched from input to output mode (Read Transfer) or output to input mode (Write Transfer/Pseudo Write Trasfer). During a data transfer cycle, the row A0-A8 select one of the 512 rows of the memory array to or from which data will be transferred and the column address A0-A8 select one of the tap locations in the serial register. The selected tap location is the start position in the SAM port from which the first serial data will be read out during the subsequent serial read cycle or the start position in the SAM port into which the first serial data will be written during the subsequent serial write cycle. Read Transfer Cycle A read transfer consists of loading a selected row of data from the RAM array into the SAM register. A read transfer is invoked by holding CAS "high", DT/OE "low" and WB/WE "high" at the falling edge of RAS. The row address selected at the falling edge of RAS determines the RAM row to be transferred into the SAM. The transfer cycle is completed at the rising edge of DT/OE. When the transfer is completed, the SAM port is set into the output mode. In a read/real time read transfer of a new row of data is completed at the rising edge of DT/OE and this data becomes valid on the SIO lines after the specified access time tSCA from the rising edge of the subsequent serial clock (SC) cycle. The start address of the serial pointer of the SAM is determined by the column address selected at the falling edge of CAS. In a read transfer cycle preceded by a write transfer cycle, the SC clock must be held at a constant VIL or VIH, after the SC high time has been satisfied. A rising edge of the SC clock must not occur until after the specified delay tTSD from the rising edge of DT/OE. In a real time read transfer cycle (which is perceded by another read transfer cycle), the previous row data appears on the SIO lines until the DT/OE signal goes "high" and the serial access time tSCA for the following serial clock is satisfied. This feature allows for the first bit of the new row of data to appear on the serial output as soon as the last bit of the previous row has been strobed without any timing loss. To make this continuous data flow possible, the rising edge of DT/OE must be synchronized with RAS, CAS and the subsequent rising edge of SC (tRTH, tCTH, and tTSL/tTSD must be satisfied). The timing restriction tTSL/tTSD are 5 ns min./10 ns min..
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Semiconductor Write Transfer Cycle
MSM518121A
A write transfer cycle transfers the contents of the SAM register into a selected row of the RAM array. If the SAM data to be transferred must first be loaded through the SAM port, a pseudo write transfer operation must precede the write transfer cycles. Data transferred to SAM by read transfer cycle can be written to other address of RAM by write transfer cycle. A write transfer is invoked by holding CAS "low", WB/WE "low" and SE "low" at the falling edge of RAS. The row address selected at the falling edge of RAS determines the RAM row address into which the data will be transferred. The column address selected at the falling edge of CAS determines the start address of the serial pointer of the SAM. After the writetransfer is completed, the SIO lines are set in the input mode so that serial data synchronized with the SC clock can be loaded. When consecutive write transfer operations are performed, new data must not be written into the serial register until the RAS cycle of the preceding write transfer is completed. Consequently, the SC clock must be held at a constant VIL or VIH during the RAS cycle. A rising edge of the SC clock is only allowed after the specified delay tSRD from the rising edge of RAS, at which time a new row of data can be written in the serial register. Pseudo Write Transfer Cycle A pseudo write transfer cycle must be performed before loading data into the serial register after a read transfer operation has been excuted. The only purpose of a pseudo write transfer is to change the SAM port mode from output mode to input mode (A data transfer from SAM to RAM does not occur). After the serial register is loaded with new data, a write transfer cycle must be performed to transfer the data from SAM to RAM. A pseudo write transfer is invoked by holding CAS "high", DT/OE "low", WB/WE "low" and SE "high" at the falling edge of RAS. The timing conditions are the same as the one for the write transfer cycle except for the state of SE at the falling edge of RAS. Transfer Operation Without CAS During all transfer cycles, the CAS input clock must be cycled, so that the column address are latched at the falling edge of CAS, to set the SAM tap location. If CAS was maintained at a constant "high" level during a transfer cycle, the SAM pointer location would be undifined. Therefore a transfer cycle with CAS held "high" is not allowed. Normal Read Transfer Cycle After Normal Read Transfer Cycle Another read transfer may be performed following the read transfer provided that a minimum delay of 30 ns from the rising edge of the first clock SC is satisfied.
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Semiconductor
MSM518121A
POWER-UP
Power must be applied to the RAS and DT/OE input signals to pull them "high" before or at the same time as the VCC supply is turned on. After power-up, a pause of 200 seconds (minimum) is required with RAS and DT/OE held "high". After the pause, a minimum of 8 RAS and 8 SC dummy cycles must be performed to stabilize the internal circuitry, before valid read, write or transfer operations can begin. During the initialization period, the DT/OE signal must be held "high". If the internal refresh counter is used, a minimum 8 CAS-before-RAS initialization cycles are required instead of 8 RAS cycle. Initial State After Power-up When power is achieved with RAS, CAS, DT/OE and WB/WE held "high" the internal state of the MSM518121A is automatically set as follows. SAM port Write mask register TAP pointer ----> Input mode ----> Write mode ----> Invalid
However, the initial state can not be guaranteed for various power-up conditions and input signal levels. Therefore, it is recommended that the initial state be set after the initialization of the device is performed (200 seconds pause followed by a minimum of 8 RAS cycles and 8 SC cycles) and before valid operations begin.
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Semiconductor
MSM518121A
PACKAGE DIMENSIONS
(Unit : mm)
ZIP40-P-475-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 3.46 TYP.
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Semiconductor
MSM518121A
(Unit : mm)
SOJ40-P-400-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.70 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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